Cell density in integrated circuits (ICs) continues to increase. Within the shrinking cell footprint, vertical feature orientations are becoming more important in the path toward monolithic 3D integration. Vertically oriented features often need to be tightly controlled to within some range of z-height, for example to achieve a particular performance metric or to ensure the feature aspect ratio provided to a downstream process is suitable.
Fabrication techniques are often subtractive, so to arrive at a final feature z-height one might pattern the feature with an initial height sufficient to account for subsequent erosion of the feature. However, such a strategy directly limits the feature density and minimum cell footprint. Regardless what feature aspect ratio (e.g., vertical height:lateral space) a given patterning process can achieve, the final product metrics will suffer if some of the height or feature pitch must be sacrificed as overhead associated with feature height erosion.
Topographic Feature architectures and techniques enabling more efficient utilization of their initially patterned aspect ratio may therefore be advantageous.